The present invention relates to neurosynaptic systems, and more specifically, this invention relates to optimizing the usage of neurosynaptic cores of a neurosynaptic system.
Core-based neurosynaptic systems are built of multiple neurosynaptic cores, where the neurosynaptic cores are configured and connected to form a network. A single neurosynaptic chip contains a fixed number of neurosynaptic cores. Chips of various sizes, i.e., number of cores, can be manufactured. To implement a neurosynaptic system, one or more chips are needed. In general, it is desired to minimize the number of chips used by the system. This goal can be served by minimizing the number of cores.